65/55nm Optimized Memory IP

Mobile Semiconductor’s silicon-proven embedded SRAM technology offers optimized memory solutions for both TSMC and SMIC 65nm low-power processes. These single-port SRAM solutions are available in a range of architectures:

low voltage (LV)

high speed (HS)

high density (HD)

Mobile Semiconductor’s proprietary design and layout techniques are applied to all architectures to optimize performance while keeping die size small.

Single-port low voltage (LV) memories use high VT devices and source biasing to minimize standby currents with limited standard VT devices used when required.

Single-port high speed (HS) memories use low VT and standard VT devices to optimize the critical path and enhance performance while limiting static current.

Single-port high density (HD) memories use standard VT devices to optimize the critical path and enhance performance.

TSMC 65nm LP

Mobile Semiconductor offers an optimized TSMC 65nm LP-process single-port low voltage (LV) embedded SRAM solution.

To ensure high manufacturing yield, the Trailblaze™ software utilizes TSMC’s standard high density 6T bit cells and is consistent with TSMC’s Design for Manufacturing (DFM) guidelines for the 65nm LP process.

Mobile Semiconductor Optimized TSMC 65nm LP Architecture


Single-Port Low Voltage

Trailblaze™ Compiler Name



SP-LV-TS65LP

SMIC 65nm LL

Mobile Semiconductor’s optimized SMIC 65nm LL-process embedded single-port SRAM solutions are offered in high speed (HS) and high density (HD) architectures.

In order to ensure high manufacturing yield, the Trailblaze™ software utilizes SMIC’s standard high density 6T bit cells and is consistent with SMIC’s Design for Manufacturing (DFM) guidelines for the 65nm LL process.

Mobile Semiconductor Optimized SMIC 65nm LL Architecture


Single-Port, High Speed
Single-Port, High Density

Trailblaze™ Compiler Name



SP-HS-SM65LL
SP-HD-SM65LL

Custom Solutions

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